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IEEE Estonia Section was recognized on base of three last years of membership development performance. As a matter of fact, the ratio of IEEE members in Section to population of Estonia has reached to level of older European countries.
Still there is lot of space to increase it further 🙂
On Wednesday, 8th April 2015 14:00 at Tallinn University of Technology, room U02-102
IEEE Distinguished lecturer Prof. Visa Koivunen
Robust Estimators for Complex-Valued Multichannel Data
Prof. Visa Koivunen is the Full Professor of Signal Processing in Aalto University, Finland, since 1999. He holds the Academy Professor position. He was a Principal Investigator in SMARAD Center of Excellence in Research in 2002-2013. He was also Adjunct Full Professor, University of Pennsylvania, USA (2003-2006); Visiting Fellow, Princeton University, NJ, USA (2007, 2013-2014); and part-time Visiting Fellow, Nokia Research Center (2006-2012). His research interest include statistical, communications, sensor array and multichannel signal processing. He has published about 350 papers in international scientific conferences and journals. He co-authored the papers receiving the best paper award in IEEE PIMRC 2005, EUSIPCO’2006, EUCAP 2006 and COCORA 2012. He has been awarded the IEEE Signal Processing Society best paper award for the year 2007. He is the recipient of 2015 EURASIP Technical Achievement Award.
The election of Estonia Section officers took place electronically on 7-14 February 2015, following a call for candidates January 30th to February 5th. The voting attracted a record participation rate this year, 31%. Each position also attracted write-in candidates, which is a testament to increased volunteer activity.
The section ExCom will be the following for 2015-2016.
- Chair: Kalle Tammemäe
- Vice-Chair: Peeter Ellervee (elected in 2014)
- Treasurer: Eiko Kängsep
- Secretary: Maie Bachmann
Nomination Committee (Urmet Jänes, Olev Märtens, Arno Kolk)
From Estonia the highest number of teams so far are participating:
- six from Tallinn University of Technology (TUT),
- five from University of Tartu (UT), and
- two from Estonian IT College.
Team names have each a story to tell: 8JavaStreet, BadHash, BSOD, coderage, Edukus, here4food, Meld, MTM, Nikitiis, Raaliroimarid, Smaces, VariableMoods, WeAreHappy.
As 18 hours of total 24 has passed, the highest position of one of UT team (Raaliroimarid) has been in top 20!
All together there were 1860 teams registered around the globe.
More details: http://www.ieee.org/xtreme, also in FB: IEEEXtreme, IEEE Estonia (pictures), etc.
Final rank of Raaliroimarid is 22th!
MTM 115, Nikitiis 154, Meld 155, here4food 160, coderage 169, BSOD 172, Edukus 210, BadHash 493, 8JavaStreet 569,
Smaces 576, VariableMoods 638, WeAreHappy 852.
All teams ranked safely inside the first half of all registered to competition teams.
In Thursday, Oct. 9 at 12:00 in U03-103 (Tallinn University of Technology) will a lecture from BEC2014 invited speaker R. V. Joshi: “Climbing the VLSI Power Wall for nm Era“.
Dr. R.V. Joshi (Bio) is also Distinguished Lecturer for IEEE CAS and EDS society.
Low Power, and energy efficiency are key themes which is pushing system, software and hardware design. In order to achieve low power system, circuit and technology co-design is essential. This talk focuses on related technology and important circuit techniques for nanoscale era.
Achieving low power and high performance simultaneously is always difficult. Technology has seen major shifts from bulk to SOI and then to non-planar devices such as FinFET/Trigates.
As the technology pushes towards sub-65nm era, process variability and geometric variation in devices can cause variation in power. The reliability also plays an important role in the power-performance envelope. This talk also reviews the methodology to capture such effects and describes all the power components. All the key areas of low power optimization such as reduction in active power, leakage power, and short circuit power are covered. Usage of clock gating, power gating, longer channel, multi-Vt design, stacking, header-footer device techniques, resonant clocking and other methods are described for logic and memory.
Finally the talk summarizes key challenges in achieving low power.